GIYSCON  Placement Paper   Technical - Electronics   Karuna PG College., Hyderabad-24 Mar 2009

GIYSCON  Placement Paper   Technical - Electronics   Karuna PG College., Hyderabad-24 Mar 2009

  • Posted by  FreshersWorld 
    7 Jan, 2012

    1.Consider a circuit with N logic nets. If each net can be stuck-at either values 0 and 1, in how many ways can the circuit be faulty such that only one net in it can be faulty, and such that up-to all nets in it can be faulty?
    a. 2 and 2N
    b. N and 2^N
    c. 2N and 3^N-1
    d. 2N and 3N  

    2. Which of the following statements is/are true?

    I.       Combinational circuits may have feedback, sequential circuits do not.

    II.     Combinational circuits have a ?memory-less? property, sequential circuits do not.

    III.  Both combinational and sequential circuits must be controlled by an external clock.

    1. I only
    2. II and III only
    3. I and II only
    4. II only

    3.Consider an alternate binary number representation scheme, wherein the number of ones M, in a word of N bits, is always the same. This scheme is called the M-out-of-N coding scheme. If M=N/2, and N=8, what is the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint, consider that the number of unique words represent able in the latter representation with N bits is 2^N. Hence the efficiency is 100%)
    a. Close to 30%
    b. Close to 50%

    c. Close to 70%
    d. Close to 100%

    4.A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority of interrupts. Nested interrupts are allowed if later interrupt is higher priority than previous one. During a certain period of time, we observe the following sequence of entry into and exit from the interrupt service routine:

    1. I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end

    From this sequence, what can we infer about the interrupt routines?

    a.      I3 > I4 > I2 > I1

    b.     I4 > I3 > I2 > I1

    c.      I2 > I1; I3 > I4 > I1

    d.     I2 > I1, I3 > I4 > I2 > I1

    5. I decide to build myself a small electric kettle to boil my cup of tea. I need 200 ml of water for my cup of tea. Assuming that typical tap water temperature is 25 C and I want the water boiling in exactly one minute, then what is the wattage required for the heating element?

    [Assume: Boiling point of water is 100 C, 1 Calorie (heat required to change 1 gm of water by 1 C)= 4 joules, 1 ml of water weighs 1 gm.]

    1. Data given is insufficient
    2. 800 W
    3. 300 W
    4. 1000 W
    5. 250 W

    6.The athletics team from REC Trichy is traveling by train. The train slows down, (but does not halt) at a small wayside station that has  a 100 mts long platform. The sprinter (who can run 100 mts in 10 sec) decides to jump down and get a newspaper and some idlis. He jumps out just as his compartment enters the platform and spends 5 secs buying his newspaper that is at the point where he jumped out. He then sprints along the platform to buy idlis that is another 50 mts. He spends another 5 secs  buying the idlis. He is now  just 50 mts from the other end of the platform where the train is moving out. He begins running in the direction of the train and the only other open door in his train is located 50 mts behind the door from where he jumped. At what(uniform) speed should the train be traveled if he just misses jumping into the open door at the very edge of the platform?

                      a. Make the following assumptions

       He always runs at his peak speed uniformly
     The train travels at uniform speed
     He does not wait (other than for the idlis & newspaper) or run backwards

    b.     Data given is insufficient
    c. 4 m/s

    d.     5 m/s

    e.     7.5 m/s

    f.       10 m/s

    7.State which of the following gate combinations does not form a universal logic set:

    1. 2-input AND + 2-input OR
    2. 2-to-1 multiplexer
    3. 2-input XOR + inverter
    4. 3-input NAND

    8.In the circuit given below, the switch is opened at time t=0. Voltage across the capacitor at t=infinity is:

    a.      2V

    b.     3V

    c.      5V

    d.     7V

    9. In a given CPU-memory sub-system, all accesses to the memory take two cycles. Accesses to memories in two consecutive cycles can therefore result in incorrect data transfer. Which of the following access mechanisms guarantees correct data transfer?

    a.      A read operation followed by a write operation in the next cycle.

    b.  A write operation followed by a read operation in the next cycle.

    c.      A NOP between every successive reads & writes

    d.     None of the above

    10.An architecture saves 4 control registers automatically on function entry (and restores them on function return). Save of each registers costs 1 cycle (so does restore). How many cycles are spent in these tasks (save and restore) while running the following un-optimized code with n=5:

    1.    Void fib(int n)


              if((n==0) || (n==1)) return 1;

              return(fib(n-1) + fib(n-2));


    a.      120

    b.     80

    c.      125

    d.     128


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