CMOS Process Variations: A Critical Operation Point Hypothesis


CMOS Process Variations: A Critical Operation Point Hypothesis


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April 2, 2008 lecture by Janak H. Patel for the Stanford University Computer Systems Colloquium (EE380). Prevailing understanding of a chip's behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors are likely as we progress further down on Moore's Law. This understanding is challenged by a new hypothesis which states that in every large CMOS chip, there exist critical operations points (frequency, voltage, temperature) such that it divides the 3-D space in to two distinct spaces: Error-free operation and Massive errors. EE380 | Computer Systems Colloquium: http://www.stanford.edu/class/ee380/ Stanford Computer Systems Laboratory: http://csl.stanford.edu/ Stanford Center for Professional Development: http://scpd.stanford.edu/ Stanford University: http://www.stanford.edu/ Stanford University channel on YouTube: http://www.youtube.com/stanford/


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